An L2 Cache Architecture Supporting Bypassing for Low Energy and High Performance

Dynamically Resizable Instruction Cache: An Energy-Efficient and High-Performance Deep-Submicron Instruction Cache

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High-Performance Low-Power Cache Memory Architectures

Recent remarkable advances of VLSI technology have been increasing processor speed and DRAM capacity. However, the advances also have introduced a large, growing performance gap between processor and main memory. Cache memories have long been employed on processor chips in order to bridge the processor-memory performance gap. Therefore, researchers have made great efforts to improve the cache p...

Low-Power L2 Cache Architecture for Multiprocessor System on Chip Design

Significant portion of cache energy in a highly associative cache is consumed during tag comparison. In this paper tag comparison is carried out by predicting both cache hit and cache miss using multistep tag comparison method. A partially tagged bloom filter is used for cache miss predictions by checking the non-membership of the addresses and hotline check for cache hit prediction by reducing...

Run-Time Cache Bypassing

Phased Drowsy I-cache with On-demand Wakeup Prediction Policy for High-performance Low-energy Microprocessors

In this paper, we propose a phased drowsy instruction cache with on-demand wakeup prediction policy (called “phased on-demand policy”) to reduce the leakage and dynamic energy with less performance overhead. As in prior non-phased on-demand policy, an extra stage for wakeup is inserted before the fetch stage in pipeline. The drowsy cache lines are woken up in wakeup stage and the wakeup latency...